Architecture of Computing Systems -- ARCS 2016: 29th by Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar

By Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich

This publication constitutes the court cases of the twenty ninth foreign convention on structure of Computing platforms, ARCS 2016, held in Nuremberg, Germany, in April 2016.
The 29 complete papers offered during this quantity have been rigorously reviewed and chosen from 87 submissions. They have been geared up in topical sections named: configurable and in-memory accelerators; network-on-chip and safe computing architectures; cache architectures and protocols; mapping of purposes on heterogeneous architectures and real-time initiatives on multiprocessors; all approximately time: timing, tracing, and function modeling; approximate and energy-efficient computing; allocation: from stories to FPGA modules; natural computing platforms; and reliability elements in NoCs, caches, and GPUs.

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Extra resources for Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings

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2c that this choice has been in favour of the host in terms of performance, Processing-in-Memory Architecture for the Smart Memory Cube 27 Fig. 2. Offloading overheads in execution of the ATF kernel (a), PIM’s speed-up with/without SMC Atomic Commands [left axis] and LLC hit-rate associated with the data port of the executing CPU [right axis] (b), Host’s execution time versus cache block size (c), and effect of PIM’s TLB size on hit-rate and execution time (d) (Colour figure online). leading to an increase in the LLC hit-rate.

But, at high loads, as port contention can be high, buffer-less router will encounter heavy deflection rate, longer delay, and increased network activity, which in turn cause early saturation. So we need minimally-buffered routers, to address these issues under high loads. We target to overcome the shortcomings of buffer-less routers under high loads and minimally-buffered routers under low loads. Addressing these limitations, we propose a novel router design, CASCADE router, that intelligently chooses to operate in different modes at different congestion levels.

With this definition, contiguous memory pages which map to contiguous page-frames can be merged to build larger slices, with arbitrary sizes. Note that, any change in page-size requires rebuilding the OS and all device drivers, while slices are transparent to the OS and other devices. PIM’s memory management is done at the granularity of the slices. The first slice is devoted to PIM’s SPM, and the rest of the memory space is mapped immediately after this region. Upon a TLB miss, a data structure in DRAM called the slice-table is consulted and the translation rules are updated on a Least Recently Used (LRU) basis.

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